1. Field of the Invention
The present invention generally relates to a semiconductor memory device and a decoding method therein, and more particularly, to a fuse box capable of decoding a row/column address of a defective memory cell, a redundant address decoder including the fuse box, and a method of repairing a defective memory cell.
2. Description of the Related Art
For an increase in yield in a semiconductor memory device, a normal memory cell array and a redundancy cell array are included so that a normal memory cell in which a defect occurs (hereinafter, ‘defect cell’) can be replaced with a redundancy memory cell (hereinafter, ‘redundant cell’).
As is well known in the related technical field, a semiconductor memory device includes a redundancy circuit to replace a defect cell with a redundant cell. The redundancy circuit includes program means for programming the address of the defect cell and a predetermined control circuit for controlling the redundancy circuit. The program means has several fuses that decode the address of the defect cell through laser or electric current to replace the defect cell with the redundancy cell.
Previously, one defect cell was replaced with one redundant cell. However, this replacement is disadvantageous in that the layout areas of the program means and the redundancy circuit having the program means are greatly increased.
Accordingly, to reduce the layout area of the redundancy circuit, one redundancy global word line is used to replace one normal global word line. One normal global word line drives four sub-word lines and one redundancy global word line drives four sub-redundancy word lines.
FIG. 1 is a view of a circuit structure of a conventional redundant row address decoder that uses a poly-silicon fuse. In a redundant row address decoder 10, one normal global word line can be replaced with one redundancy global word line.
The redundant row address decoder 10 includes a plurality of transistors 1 through 57, a fuse box 30 and a redundancy word line selection circuit 40.
The redundant row address decoder 10 decodes the input row address signals DRA234, DRA56, DRA78, DRA910 and DRA112 and activates a redundancy global word line SWEi corresponding to the row address signals. When the redundancy global word line SWEi is activated, a defect cell is replaced with a redundant cell.
A pair of complimentary signals RES and RESB that control the redundancy row address decoder 10 are generated from a redundancy control signal generation circuit (not shown). When a redundancy operation is performed, a redundancy enable signal RES is activated and as a result, transistors 1 through 27 which transmit the address signals DRA234, DRA56, DRA78, DRA910 and DRA112 of the defect cell, are turned on. However, during normal operations, transistors 49, 51, 53, 55 and 57 are turned on in response to the activated complementary redundancy enable signal RESB and, therefore, the redundancy global word line SWEi is inactivated.
The fuse box 30 includes a plurality of fuses F1 through F24. The plurality of fuses F1 through F24 are poly-silicon fuses which can be cut with a laser or electric current and are selectively cut to represent the address of the defect cell.
The redundancy word line selection circuit 40 includes a plurality of inversion circuits 59, 61 and 63 and an NOR gate 65, as shown in FIG. 1.
A case when one redundancy global word line SWEi is selected will be described now with respect to FIG. 1. Fuses F2 through F9, F11 through F13, F15 through F18 and F20 through F23 are cut when the redundancy enable signal RES is activated, the address DRA234 of the defect cell is <000>, the address DRA78 is <01>, the address DRA910 is <10>and the address DRAL 112 is <11>. As a result, the address of the defect cell is decoded by the fuse box 30.
The redundancy word line selection circuit 40 responds to signals of nodes N6 through N10, e.g., logic ‘high’, and outputs the activated redundancy global word line enable signal SWEi to a redundancy word driver (not shown). The redundancy word driver responds to the activated redundancy global word line enable signal SWEi and activates four sub-redundancy word lines connected to the redundancy global word line.
However, while one normal global word line is replaced with one redundancy global word line, normal memory cells of a plurality of memory cells connected to one normal global word line may also be replaced with redundant cells, thus deteriorating product characteristics.
FIG. 2 is a plan view of the layout of the fuse box shown in FIG. 1. Referring to FIG. 2, in a conventional fuse box 30, twenty-four fuses F1 through F24 are laid out on an area of 83.7 μm in width and 12.79 μm in length considering a distance between fuses which are capable of decoding the row address of the defect cell (the distance is called ‘fuse pitch’). Each of the addresses DRA234, DRA56, DRA78, DRA910 and DRAL112 are input to the twenty-four fuses F1 through F24 through the transistors 1 through 47.
However, the layout area of the conventional fuse box 30 can be reduced only within a limited range because there is a limitation in reducing the fuse pitch. Also, during replacing one normal global word line with one redundancy global word line, normal memory cells connected to one normal global word line may also be replaced with redundant cells, thus decreasing redundancy efficiency.